A potential project for RetroChallenge:
Overclock the main memory bus of a SPARCstation-10, by replacing the 80MHz master oscillator with a 90MHz one. This would up the memory-bus clock from 40MHz to 45MHz.
Most SPARCstation-10 CPUs run asynchronously to the memory bus, so this will not increase CPU clock-frequency. However, when you are running 180MHz CPUs on a 40 MHz in-order memory-bus, the main performance bottleneck is the memory bus, which is also used for inter-processor synchronisation and as a bridge to the main I/O bus; so it is a worthwhile enhancement.
Difficulty Rating: if it can be done at all, and if a suitable crystal oscillator can be obtained: pretty easy.
The difficulties involved in this projrect are that the replacement crystal oscillator needs to have 5V TTL/HCMOS-compatible output, be extremely accurate with low jitter, although it does not need an extremely high duty-cycle (anything from 25% to 75% would suffice according to the SS10 chipset datasheets). Also, I am not sure whether a 90MHz fundamental frequency crystal is needed, or whether a 3rd-overtone at 90MHz would suffice. It will also be necessary to determine whether an oscillator with pin-selectable enable/disable capability is needed.
This frequency enhancement would also cause the System Memory Controller (SMC) to run outside it’s specified limit. It would also possibly overstress standard SS10 80ns memory modules, fortunately my SS10 is fitted with 60ns memory modules.
The resulting overclock of the SBus from 20MHz to 22.5MHz should not be a problem: apart from the *very* oldest SBus cards (1987-1989), all should work upto the specified SBus maximum of 25MHz, and I’m hoping thet the version of the onboard MSI (MBus/SBus bridge) is specified upto 50/25MHz, and that the Clock2 chip revision is rated for upto 100MHz input (I believe so, but will have to check – or nick one from an SS20!).